Verilog testbench common blocks

1. System function block
Read in the local file, the last two can default

$readmemb ("<Data file name>",<Repository name>,<Start address>,<End address>)
$readmemh ("<DataFileName>",<RepositoryName>,<StartAddress>,<EndAddress>)

reg [379:0] CAL2_sample[0:2999];
initial $readmemb ( "./../matlab/ideal_high_freq_sample_bits.txt", CAL2_sample,0,2999 );

tdc_finecode_i <= CAL2_sample[samlpe_cnt];

Save the print results to the document

// finetime_o finetime_valid_o output:dut
integer fid;
initial
	fid = $fopen("fintimeout_ideal1.txt","w");
	
integer finetime_cnt=0;
[email protected](posedge main_pll_clk_80m_i or negedge rst_n) begin
	if(!rst_n) begin
		finetime_cnt <= 'd0;
	end
	else if(finetime_cnt==2999) 
		$fclose(fid); 
	else if(finetime_valid_buf==2'b01) begin
		finetime_cnt <= finetime_cnt + 1'b1; 
		$fwrite(fid,"%d\n",finetime_o); 
		$display("%d",finetime_o);
	end 
	finetime_valid_buf <= {finetime_valid_buf[0],finetime_valid_o};
end


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