Tag Archives: quartus

[Solved] Quartus II waveform simulat error: error: waveform2 vwf. VT (30): near “,” syntax error, unexpected “, ‘# * * error

I. problem
when quartus is used to design 4 frequency divider based on D trigger, the following errors occur in waveform simulation:

 Error: Waveform2.vwf.vt(30): near ",": syntax error, unexpected ','
# ** Error: D:/Quartus/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./D4.do line 4
Error.

II. Solution

in the schematic design, my input and output ports are named input and output respectively. That’s the mistake. We just have to name it something else. For example: CLKIN, out. Then recompile and no error will be reported during simulation. The correct simulation diagram is as follows:

[Solved] Error: Waveform5.vwf.vt(30): near “1“: syntax error, unexpected INTEGER NUMBER, expecting ‘)‘ Erro


Error: Waveform5.vwf.vt(30): near “1”: syntax error, unexpected INTEGER NUMBER, expecting ‘)’
Error: e:/quartus/modelsim_ase/win32aloem/vlog failed.
Executing ONERROR command at macro ./deng01.do line 4

Solution:
1:Change the output port output to another name
2:The beginning of the input name cannot be a number

Quartus compile error: Error (10170): Verilog HDL syntax error at Verilog1.v(8)

Codes:
module adder(
input [31:0] operand1,
input [31:0] operand2,
input cin,
output [31:0] result,
output cout
);
assign {cout,result} = operand1 + operand2 + cout;
endmodule

 

Error Messages:

Error (10170): Verilog HDL syntax error at Verilog1.v(8) near text: “cout”; expecting “highz0”, or “highz1”, or “large”, or “medium”, or “pull0”, or “pull1”, or “small”, or “strong0”, or “strong1”, or “supply0”, or “weak0”, or “weak1”. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10759): Verilog HDL error at Verilog1.v(8): object result declared in a list of port declarations cannot be redeclared within the module body
Error (10112): Ignored design unit “adder” at Verilog1.v(1) due to previous errors
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning
Error: Peak virtual memory: 4702 megabytes
Error: Processing ended: Sat Nov 27 15:57:22 2021
Error: Elapsed time: 00:00:12
Error: Total CPU time (on all processors): 00:00:27
Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning


Solution:

Select the option in the red box.

Done!

Error (12153): Can‘t elaborate top-level user hierarchy

This error message appears when quartus is integrating
find the corresponding code:

from the sensitive list, the register in the always block is asynchronously reset, so during synthesis, the reset end of the register must only be connected with the reset signal, but the code is connected with the synchronization signal other than the reset signal
modification method:
1. Change to synchronization

always@(posedge clk) begin
	if(!rst_n || first_tu_flag) begin
		...
	end

2. Standard writing

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		...
	end
	else if(first_tu_flag) begin
		...
	end

When using quartus for function simulation, “testbench” appears_ vector_ input_ The solution of “file option does not exist”

Environment: quartus 18 prime Standard Edition

1. Create a new VMF file

Add node or bus

2. Click processing – & gt; start – & gt; start test bench template writer, and a. VHT suffix file will be generated under the path of “project folder/simulation/Modelsim” (the path may be different due to different personal settings).

3. Copy the. VHT suffix file in the path of “project folder/simulation/Modelsim” to the path of “project folder/simulation/QSIM”.

4. Open the vWF file created in step 1, click simulation – & gt; simulation settings, and the following interface will appear. Modify the contents in the functional simulation settings tab as follows (note that the direction of path separator in quartus software is opposite to that in windows, one is’/’, the other is’ \’):

(1) Change “- vector” in the testbench generation command (functional simulation) column to_ Change the path after “source” to the path of your own VWF file (note that the file name should also be changed to the name of your own file), “– testbench_ Change the path after “file” to the path of the. VHT suffix file copied in step 3 (note that the file name should also be changed to your own file name);

(2) Change “- output” in the netlist generation command (functional simulation) column_ The path after “directory” is changed to “project folder/simulation/QSIM”.

(3) Add VCOM – work in the Modelsim script (functional simulation) column Waveform.vwf.vht Change the file name to your own.

(4) If you want to do timing simulation, modify the contents of the timing simulation settings tab.

5. Finished, add input data and click simulation.