This error message appears when quartus is integrating
find the corresponding code:

from the sensitive list, the register in the always block is asynchronously reset, so during synthesis, the reset end of the register must only be connected with the reset signal, but the code is connected with the synchronization signal other than the reset signal
modification method:
1. Change to synchronization

always@(posedge clk) begin
	if(!rst_n || first_tu_flag) begin
		...
	end

2. Standard writing

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		...
	end
	else if(first_tu_flag) begin
		...
	end