In the process of program synthesis using Vivado, errors are reported in full compilation, as shown below:
[Chipscope 16-302]Could not generate core for dbg_hub.Aborting IP Generate operaion.The current Vivado temporary directory path. ............
Error reason: 
The project folder name is too long. Shorten the project folder name as shown in the following figure.
Solution:
Shorten the project folder name and recompile it.
petalinux-build Error: ERROR: Task (/opt/pkg/petalinux/components/yocto/source/aarch64/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_compile) failed with exit code ‘1’
as below:
co@nvdla:~/petaproj/nvdla$ petalinux-build
[INFO] building project
[INFO] sourcing bitbake
[INFO] generating user layers
INFO: bitbake petalinux-user-image
Loading cache: 100% |############################################| Time: 0:00:00
Loaded 3811 entries from dependency cache.
Parsing recipes: 100% |##########################################| Time: 0:00:03
Parsing of 2777 .bb files complete (2775 cached, 2 parsed). 3812 targets, 150 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#######################################| Time: 0:00:02
Checking sstate mirror object availability: 100% |###############| Time: 0:00:11
Sstate summary: Wanted 174 Found 9 Missed 330 Current 757 (5% match, 82% complete)
NOTE: Executing SetScene Tasks
NOTE: Executing RunQueue Tasks
ERROR: fsbl-2019.1+gitAUTOINC+26c14d9861-r0 do_compile: Function failed: do_compile (log file is located at /home/co/petaproj/nvdla/build/tmp/work/plnx_zynqmp-xilinx-linux/fsbl/2019.1+gitAUTOINC+26c14d9861-r0/temp/log.do_compile.899)
ERROR: Logfile of failure stored in: /home/co/petaproj/nvdla/build/tmp/work/plnx_zynqmp-xilinx-linux/fsbl/2019.1+gitAUTOINC+26c14d9861-r0/temp/log.do_compile.899
Log data follows:
| DEBUG: Executing shell function do_compile
| aarch64-none-elf-gcc -MMD -MP -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects -c xfsbl_board.c -o xfsbl_board.o -Izynqmp_fsbl_bsp/psu_cortexa53_0/include -I.
| In file included from xfsbl_board.c:54:
| xfsbl_board.h:64:10: fatal error: xiicps.h: No such file or directory
| #include "xiicps.h"
| ^~~~~~~~~~
| compilation terminated.
| make: *** [Makefile:34: xfsbl_board.o] Error 1
| WARNING: /home/co/petaproj/nvdla/build/tmp/work/plnx_zynqmp-xilinx-linux/fsbl/2019.1+gitAUTOINC+26c14d9861-r0/temp/run.do_compile.899:1 exit 2 from 'make'
| ERROR: Function failed: do_compile (log file is located at /home/co/petaproj/nvdla/build/tmp/work/plnx_zynqmp-xilinx-linux/fsbl/2019.1+gitAUTOINC+26c14d9861-r0/temp/log.do_compile.899)
ERROR: Task (/opt/pkg/petalinux/components/yocto/source/aarch64/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 2926 tasks of which 2910 didn't need to be rerun and 1 failed.
Summary: 1 task failed:
/opt/pkg/petalinux/components/yocto/source/aarch64/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_compile
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
ERROR: Failed to build project
Solution:
1) File Directory <petalinux_proj>/project-spec/meta-user/recipes-bsp/fsbl/fsbl_%.bbappend
Check whether there is fsbl_% Bbappend or not, create it if not:
vim <plnx-proj-root>/project-spec/meta-user/recipes-bsp/fsbl/fsbl_%.bbappend2) Add the following
do_compile_prepend(){
install -m 0644 ${TOPDIR}/../project-spec/hw-description/psu_init.c ${B}/fsbl/psu_init.c
install -m 0644 ${TOPDIR}/../project-spec/hw-description/psu_init.h ${B}/fsbl/psu_init.h
}3) Clean up and rebuild the fsbl file
$ petalinux-build -c fsbl -x cleanall
$ petalinux-build -c fsblProblem-solving!
Problem phenomenon
When installing Xilinx_SDK on Linux system, the second step is to enter the Xilinx account name and password, if you don’t have the account name and password, you can click “please create one” in the interface to create one. However, the problem is that after creating the Xilinx user correctly, the software cannot be installed properly, and the error is as follows
The root cause of this problem is that there are still unfilled user information when registering Xilinx accounts. The solution is as follows:
Problem-solving:
Log in to the official Xilinx website with the registered Xilinx account, and then enter the download station as shown in the following figure:
Find something to download. If the account is short of something, you will be prompted to fill in the information. The interface is as follows:
After these information are filled in and submitted, if the selected software can be downloaded normally, it is proved that the personal information missing from Xilinx account is completed.
At this point, back to the Xilinx_SDK installation interface, you can use the registered Xilinx account to install normally, and successfully enter the third page of the following figure.
After selecting the content and path to install, you can install normally, as shown in the following figure:
When compiling VIVADO project, you will encounter the error: Spawn failed：No error
This is a bug in vivado. After other errors are eliminated, this error will appear and prevent compilation.
Solution:
Just click the trash can next to the error prompt on the messages interface.
Openfpga environment configuration and problem-solving
Environment configuration process
git clone https://github.com/LNIS-Projects/OpenFPGA.git
cd OpenFPGA/.github/workflows
# Add ‘sudo’ before apt-get in script: install_depencies_build.sh
source install_depencies_build.sh # (install all depencies)
# back to OpenFPGA
python3 –m pip install –r requirements.txt
make all
# During make, watch the error messages and see which package is missing, repeatly using ‘sudo apt install XXX’ to install them like:
Tcl.h: sudo apt install tcl-dev
readline: sudo apt install readline-dev
Compilation error
SIGSTKSZ Error
1. Download
wget -O ~/Downloads/catch.hpp https://github.com/catchorg/Catch2/releases/download/v2.13.9/catch.hpp
2. Replace the file
cd {OpenFPGA_File_location}/libs/EXTERNAL/libcatch/
mv catch.hpp catch.bak.hpp
mv ~/Downloads/catch.hpp ./
wget -O ~/Downloads/tbb_stddef.h https://raw.githubusercontent.com/wjakob/tbb/9e219e24fe223b299783200f217e9d27790a87b0/include/tbb/tbb_stddef.h
sudo mv ~/Downloads/tbb_stddef.h /usr/include/tbb
Missing header file task_scheduler_init.h
wget -O ~/Downloads/task_scheduler_init.h https://raw.githubusercontent.com/wjakob/tbb/raw/master/include/tbb/task_scheduler_init.h
sudo mv ~/Downloads/task_scheduler_init.h /usr/include/tbb
Dependency not found
Note
# Missing ffi.h
sudo apt install libffi-dev
# Missing tcl.h
sudo apt install tk tcl tk-dev tcl-dev
# Missing readline
sudo apt install readline-dev libreadline6-dev
run-task error
Check the log. The most observed problem is that envYAML package is not installed
pip3 install envyaml
ModuleNotFoundError ‘prettytable’
When running run_vtr_task.py, it prompts: ModuleNotFoundError: No module named ‘prettytable’
processing:
# update pip
python -m pip install --upgrade pip
# install PrettyTable package
pip install PrettyTable
Script unsatisfiable
Network environment problems
include:
Solution:
Runtime problems
Permission Denied | Can not find directory…
Problem Analysis: The command is incorrectly run with the root user when git clone or install dependencies, resulting in the personal user not having any modification rights.
Solution: In the root directory of OpenFPGA
sudo chown -hR {user name}:{user group, usually same as user name} . /
# Change all file owners to individual users
In the yosys shell, when the show command views the circuit diagram, it prompts an error
Problem: lack of dot matrix graphic display tool
solution: try running sudo apt-get install xdot
Problem description
When SDRAM initializes the module simulation, other modules are used. If the compilation is correct, the simulation will report an error:
Instantiation of ‘sdram_model_plus’ failed. The design unit was not found.
Solution:
Add files at the same time, and the name is the same to the tb file.
If you don’t find the file, you can add one of them. Just note that the name in the red box above is the same to the tb file.
ERROR: [IMPL 213-28] Failed to generate IP.
Questions
Vivado HLS C has been integrated and verified by functional simulation, but IP cannot be generated
Solution:
Modify the system time to 2021 or before
Seconds after modification succeeded
Vivado installation error: Xilinx design tool, already exists for 2019.2, specify a different program program group entry 
Reason for error: vivado has been installed, and Xilinx Design Tools folder already exists
Solution: find the “Xilinx Design Tools” folder and delete it
Xilinx Design Tools folder path: C:\USER\USERNAME\AppData\Roaming\Microsoft\Windows\Start Menu\Programs
Error Messages:
Error “memory write error at 0x100000.apb AP transaction error, DAP status f0000021” occurred during zynq burning
How to Solve:
In the first contact with zynq, when using PL side resources with bit stream hardware data, the following configuration was not selected when burning the software, resulting in the error prompt shown in the title.
when the option shown in the above figure is checked, the bit stream data will be burned first and the FPGA will be configured, as shown in the following figure. Then it runs normally
Error while launching program:
Memory write error at 0x100000. APB Memory access port is disabled
This error occurs because the DDR model is not selected correctly. Just check the DDR model.
One is the data width of DDR. If it is a single chip, it is generally 16 bits, and two chips are generally 32 bits.
quartus 13 利用IP核 NCO 生成dds出现Megawizard error解决
The following errors occurred when using NCO in IP core to produce DDS:
MegaWizard Error MegaCore Function Generation Error IP Functional Simulation Model Creation Failed. The following error was returned;Error: Quartus ll 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings
I checked many methods on the Internet and cracked the IP core, but the problem still appears when quoting the IP core. After my actual measurement, it may be due to the problem of version 13.
Suggestion: it may be due to the problem with version 13. After installing version 18 of quartus, I can normally use fir # NCO and other IP cores
You can see that I modified the values of clock rate and desired output freq, but the waveform of the following magnet has not changed, but my IP core has been cracked.
After installing Quartus # 18, you can see that the magnetic waveform has a pulse at 6mhz, which is consistent with the output frequency we designed
Ibufg reports an error during compilation
ERROR :;NgdBuild:770 - IBUFG ‘IBUFG_inst4’ and IBUFG ‘PLL_doub_u/clkin1_buf’ on net ‘clk_pll’ are lined up in series. Buffers of the same direction cannot beplaced in series. ERROR:NgdBuild:462 - input pad net ‘clk pll’ drives multiple buffers: pin o on block IBUFG_inst4 with type IBUFG, pin I on block PLL_doub_u/ clkin1_buf with type IBUEG.
Ibufg error analysis
The first error says that the buffer has the same point
The second error refers to multiple buffer conflicts on the clock pin clk_pll that I have defined.
map compilation failed
Solution:
This error is caused by adding buffer to the input clock source in the IP core of PLL
after modifying to no buffer, we can use our global ibufg