ESP8266 Chip sync error esp_sync_blocking.

ESP8266 firmware continues to fail and displays chip Sync Error
View pin definition
|Function| URXD>0 UART_RXD, receive
>1 UTXD b>2 UART_TXD, send
>3 RST>4 external Reset signal, low level Reset, high level work (default high)
>5 GND>6 GND
>7 VCC>8 3.3v, module power supply
>9 GPIO 0>0 working mode Drop down: UARTDownload, download mode
|CH_PD | high level operation;
|GPIO 2 | (1) power on must be high level, do not pull down the hardware; (2) Internal default has been elevated
RST pin ground reset after re-burning, successful
Timed out waiting for Packet Header
Solution: RST pin needs to be connected until it turns up a connecting connecting wire, unplug RST ground wire and upload successfully

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