Ibufg reports an error during compilation
ERROR :;NgdBuild:770 - IBUFG ‘IBUFG_inst4’ and IBUFG ‘PLL_doub_u/clkin1_buf’ on net ‘clk_pll’ are lined up in series. Buffers of the same direction cannot beplaced in series. ERROR:NgdBuild:462 - input pad net ‘clk pll’ drives multiple buffers: pin o on block IBUFG_inst4 with type IBUFG, pin I on block PLL_doub_u/ clkin1_buf with type IBUEG.
Ibufg error analysis
The first error says that the buffer has the same point
The second error refers to multiple buffer conflicts on the clock pin clk_pll that I have defined.
map compilation failed
This error is caused by adding buffer to the input clock source in the IP core of PLL
after modifying to no buffer, we can use our global ibufg
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