Tag Archives: verilog

Quartus compile error: Error (10170): Verilog HDL syntax error at Verilog1.v(8)

Codes:
module adder(
input [31:0] operand1,
input [31:0] operand2,
input cin,
output [31:0] result,
output cout
);
assign {cout,result} = operand1 + operand2 + cout;
endmodule

 

Error Messages:

Error (10170): Verilog HDL syntax error at Verilog1.v(8) near text: “cout”; expecting “highz0”, or “highz1”, or “large”, or “medium”, or “pull0”, or “pull1”, or “small”, or “strong0”, or “strong1”, or “supply0”, or “weak0”, or “weak1”. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10759): Verilog HDL error at Verilog1.v(8): object result declared in a list of port declarations cannot be redeclared within the module body
Error (10112): Ignored design unit “adder” at Verilog1.v(1) due to previous errors
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning
Error: Peak virtual memory: 4702 megabytes
Error: Processing ended: Sat Nov 27 15:57:22 2021
Error: Elapsed time: 00:00:12
Error: Total CPU time (on all processors): 00:00:27
Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning


Solution:

Select the option in the red box.

Done!

After vivado joined ILA, the [DRC lutlp-1] problem of error problem was solved

        This article is a summary of my study. If there are copyright or knowledge errors or problems, please contact me directly. Please leave a message
         PS: Based on the principle of knowledge sharing, this blog can be reproduced, but please indicate the source!

catalogue

1. Problem description

2. Cause analysis:

  3. Problem solving:

1. Problem description

         When I debug the project, in order to capture the signal value to observe the timing, I added ILA, and then encountered vivado error when generating bitstream. The warning is as follows:

  The specific error contents are as follows:

[DRC LUTLP-1] Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop. 
This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is u_DdrRdData/NxtRdState[0]. Please evaluate your design. The cells in the loop are: u_DdrRdData/NxtRdState_inferred_i_3, and u_DdrRdData/NxtRdState_inferred_i_8.

2. Cause analysis:

        As shown in the code segment below, the combinational loop is combinational logic, which feeds back to itself without registers. The simplest example is an inverter whose output is fed back to the input to produce an oscillator.

         Therefore, the combined logic signal nxtrdstate for the state machine cannot be used for ILA grabbing!!!

  At the same time, the error can be prompted in the warning message of vivado tool:

This warning is described in ug901 as follows:

  3. Problem solving:

         Do not use ILA to grab the signal value assigned in the combinatorial logic of the state machine!!!

Error (12153): Can‘t elaborate top-level user hierarchy

This error message appears when quartus is integrating
find the corresponding code:

from the sensitive list, the register in the always block is asynchronously reset, so during synthesis, the reset end of the register must only be connected with the reset signal, but the code is connected with the synchronization signal other than the reset signal
modification method:
1. Change to synchronization

always@(posedge clk) begin
	if(!rst_n || first_tu_flag) begin
		...
	end

2. Standard writing

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		...
	end
	else if(first_tu_flag) begin
		...
	end

When vivado2017 is started, the “error when launching” dialog box will pop up vivado.bat : Launcher time out”

If oxc000007b error occurs at this time, it is because 32bit DLL is used in 64 bit OS. It is generally caused by the wrong use of vcomp140.dll.

Slove problem：

    Enter https://cn.dll-files.com Search and download the required DLL (mainly its own system bit 32 / 64) and copy the DLL to the directory according to the instructions
    on 64 bit windows,
    the default path of 32-bit DLL file is C: (Windows) syswow64
    the default path of 64 bit DLL file is C: (Windows) system32 \
on 64 bit windows