Stm32f4 mdk5 software simulation error: no ‘read’ permission
mdk5 software simulation prompts that you have no read-write permission and can only run step by step. The prompt code is as follows:
*** error 65: access violation at 0x40023800 : no 'read' permission *** error 65: access violation at 0x40023800 : no 'write' permission *** error 65: access violation at 0x40023808 : no 'write' permission *** error 65: access violation at 0x40023800 : no 'read' permission *** error 65: access violation at 0x40023800 : no 'write' permission
The root cause is: there is a problem with the map address space permission mapping. Some address spaces do not have read and write permissions, resulting in the program can not run automatically.
Add map address space permission mapping
according to the introduction of network resources, there are three methods:
1 Modify the debug tab in the project configuration option, and stm32f1 series chip verification can be used normally. F4 series chips cannot be used normally
2. Modify the map address permission mapping directly on the debugging page. After normal modification, the program can run normally. It needs to be reset when exiting debugging, which is inconvenient to operate
3. In the debug tab of the project configuration options, add the correct initialization file directly. (recommended)
Create a new “debug.ini” file in the project file, and add the map address permission mapping code in the file
map 0x40000000, 0x40007FFF read write // APB1 map 0x40010000, 0x400157FF read write // APB2 map 0x40020000, 0x4007FFFF read write // AHB1 map 0x50000000, 0x50060BFF read write // AHB2 map 0x60000000, 0x60000FFF read write // AHB3 map 0xE0000000, 0xE00FFFFF read write // CORTEX-M4 internal peripherals
The specific map address permission mapping can also be viewed in the memory map option in the debugging interface.
On the debug page, select the memory map option under the debug tab, as shown below
Map address mapping can be added according to the error prompt.
Relevant parameters are mainly configured according to the model of Engineering chip
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