Tag Archives: vitis

Petalinux-boot –jtag error [How to Solve]

petalinux-boot –jtag –u-boot –hw_server-url TCP:ubuntu:3121
Using the command as above will report an error similar to the one below.

Solution:
Set the compatibility of the virtual machine’s USB device to USB3.1, because the physical USB port my computer is connected to is USB3.1.

INFO: Sourcing build tools
INFO: Launching XSDB for file download and boot.
INFO: This may take a few minutes, depending on the size of your image.
rlwrap: warning: your KaTeX parse error: Expected ‘EOF’, got ‘#’ at position 170: … “name =~ “arm*#̲0″”. available …params(filter)”. available targets:$target_list””
(procedure “targets” line 177)
invoked from within
“targets -set -nocase -filter {name =~ “arm*#0”}”
(file “/tmp/tmp.tUZ8sEM2Wm” line 3)
INFO: The XSDB log is as follows

Memory write error at 0x100000. MMU section translation fault [How to Solve]

The following error is reported when debugging the MZ702P board using vitis2020.2 JTAG.
The reason is that the boot mode is not set to JTAG boot.

Downloading Program – F:/FPGA/Project/vitis_workspace/helloWorld/Debug/helloWorld.elf
section, .text: 0x00100000 - 0x00100a1f
section, .init: 0x00100a20 - 0x00100a2b
section, .fini: 0x00100a2c - 0x00100a37
section, .rodata: 0x00100a38 - 0x00100a77
section, .data: 0x00100a78 - 0x00100ee7
section, .eh_frame: 0x00100ee8 - 0x00100eeb
section, .mmu_tbl: 0x00104000 - 0x00107fff
section, .init_array: 0x00108000 - 0x00108003
section, .fini_array: 0x00108004 - 0x00108007
section, .bss: 0x00108008 - 0x0010802f
section, .heap: 0x00108030 - 0x0010a02f
section, .stack: 0x0010a030 - 0x0010d82f
0% 0MB 0.0MB/s ??:??ETA
aborting, 2 pending requests…
aborting, 1 pending requests…
Failed to download F:/FPGA/Project/vitis_workspace/helloWorld/Debug/helloWorld.elf
Memory write error at 0x100000. MMU section translation fault

or report the error below:

21:50:53 INFO : Checking for BSP changes to sync application flags for project ‘helloWorld’…
21:51:32 INFO : Connected to target on host ‘127.0.0.1’ and port ‘3121’.
21:51:32 INFO : Jtag cable ‘Digilent JTAG-HS1 210249856275’ is selected.
21:51:32 INFO : ‘jtag frequency’ command is executed.
21:51:32 INFO : Context for ‘APU’ is selected.
21:51:32 INFO : System reset is completed.
21:51:35 INFO : ‘after 3000’ command is executed.
21:51:35 INFO : Context for ‘APU’ is selected.
21:51:35 INFO : Hardware design and registers information is loaded from ‘F:/FPGA/Project/vitis_workspace/MZ702P/export/MZ702P/hw/MZ702P_wrapper.xsa’.
21:51:35 INFO : ‘configparams force-mem-access 1’ command is executed.
21:51:35 INFO : Context for ‘APU’ is selected.
21:51:35 INFO : Sourcing of ‘F:/FPGA/Project/vitis_workspace/helloWorld/_ide/psinit/ps7_init.tcl’ is done.
21:51:36 ERROR : Memory read error at 0xE0001034. AP transaction timeout
21:51:36 INFO : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -nocase -filter {name =~“APU*”}
rst -system
after 3000
targets -set -nocase -filter {name =~“APU*”}
loadhw -hw F:/FPGA/Project/vitis_workspace/MZ702P/export/MZ702P/hw/MZ702P_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}] -regs
configparams force-mem-access 1
targets -set -nocase -filter {name =~“APU*”}
source F:/FPGA/Project/vitis_workspace/helloWorld/_ide/psinit/ps7_init.tcl
ps7_init
----------------End of Script----------------
21:51:36 ERROR : Memory read error at 0xE0001034. AP transaction timeout

Xilinx Vitis Error Launching Program: Memory write error MMU section translation fault

Run As -> Launch Hardware (Single Application Debug (GDB))  Error:
Error while launching program:
Memory write error at 0x100000. MMU section translation fault

The reason is that the JP4 interface is mistakenly connected to SD, but it can be connected to JTAG and the Program Device can be successfully connected.

 

Xilinx Vitis arm-xilinx-eabi-gcc.exe: error: *.c: Invalid argument

This problem may be a bug of version 2021.1 only. Unfortunately, I’m just currently using this version.
After Build Project:

Find where this Makefile is through “make: Leaving directory” information. For me, it is located at  Zynq_CPU_wrapper_hw_platform_1\zynq_fsbl\zynq_fsbl_bsp\ps7_cortexa9_0\libsrc\rtl_multiplier_v1_0\src\Makefile (we assume Zynq_CPU_wrapper_hw_platform_1 is the platform name and is under the Vitis workspace folder). Locate this file, we see the following code:

COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o

libs:
	echo "Compiling rtl_multiplier..."
	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
	make clean

include:
	${CP} $(INCLUDEFILES) $(INCLUDEDIR)

clean:
	rm -rf ${OUTS}

According to
Drivers created in Vivado fail in Vitis 2021.1https://support.xilinx.com/s/question/0D52E00006ihQSXSA2/drivers-created-in-vivado-fail-in-vitis-2021175527 – Drivers created in Create or Import Wizard in Vivado fail in Vitishttps://support.xilinx.com/s/article/75527
and damiet’s answer inVitis IDE 2021.1 custom AXI IP core compile errorhttps://support.xilinx.com/s/question/0D52E00006hpYgWSAU/vitis-ide-20211-custom-axi-ip-core-compile-errorNote if we do not modify LIBSOURCES as instructed above, there will be still an error pointing to the same line because it requires $(LIBSOURCES):

We modify the Makefile as:

COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=*.h
LIBSOURCES=$(wildcard *.c)
OUTS = *.o
OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))

libs:
	echo "Compiling rtl_multiplier..."
	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} ${ASSEMBLY_OBJECTS}
	make clean

include:
	${CP} $(INCLUDEFILES) $(INCLUDEDIR)

clean:
	rm -rf ${OBJECTS} ${ASSEMBLY_OBJECTS}

We only modify LIBSOURCES, add OBJECTS and ASSEMBLY_OBJECTS, and replace $(OUTS) at $(ARCHIVER) line and rm -rf line with $(OBJECTS) $(ASSEMBLY_OBJECTS). If you go through Makefile under other directories under libsrc, like Zynq_CPU_wrapper_hw_platform_1\zynq_fsbl\zynq_fsbl_bsp\ps7_cortexa9_0\libsrc\cpu_cortexa9_v2_11\src\Makefile, you will see how is this patch invented.
This time building goes further, but still fails:

and two identical pop-up windows:

By adding echo, we found that this error is no longer caused by the Makefile we modified before. Reading information given by Build Console carefully, we found the following information:

‘Finished building libraries’
make: Leaving directory ‘D:/Documents/GitHub/ECE4810J_FA2021/Lab1/Zynq_CPU_wrapper_hw_platform_1/zynq_fsbl/zynq_fsbl_bsp’
arm-none-eabi-gcc -o fsbl.elf  sd.o  nand.o  image_mover.o  md5.o  fsbl_hooks.o  main.o  nor.o  qspi.o  rsa.o  ps7_init.o  pcap
.o  fsbl_handoff.o -MMD -MP       -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard   -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard –
Wl,-build-id=none -specs=Xilinx.spec  -lrsa -Wl,–start-group,-lxil,-lgcc,-lc,–end-group -Wl,–start-group,-lxilffs,-lxil,-lgc
c,-lc,–end-group -Wl,–start-group,-lrsa,-lxil,-lgcc,-lc,–end-group                                    -Wl,–gc-sections -Lzy
nq_fsbl_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld
Building the BSP Library for domain  – standalone_ps7_cortexa9_0 on processor ps7_cortexa9_0
make –no-print-directory seq_libs
“Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src”
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include  “SHELL=CMD” “COMPILER=arm-none-eabi-gcc” “ASSEMBLER=arm-none
-eabi-as” “ARCHIVER=arm-none-eabi-ar” “COMPILER_FLAGS=  -O2 -c” “EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=h
ard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns”

For me, it is located at Zynq_CPU_wrapper_hw_platform_1\ps7_cortexa9_0\standalone_ps7_cortexa9_0\bsp\ps7_cortexa9_0\libsrc\rtl_multiplier_v1_0\src\Makefile. Its contents are identical to the contents of the previous Makefile.
Interestingly, another same Makefile Zynq_CPU_wrapper_hw_platform_1\hw\drivers\rtl_multiplier_v1_0\src\Makefile does not cause any errors.
After done that, we can see the qemu_args.txt error mentioned by Programaths’s answer in
Vitis 2021.1 error Makefilehttps://support.xilinx.com/s/question/0D52E00006hpRo8SAE/vitis-20211-error-makefile

10:48:42 **** Incremental Build of configuration Debug for project hello_rtl_multiplier_system ****
make all 
Generating bif file for the system project
generate_system_bif.bat 1453 D:/Documents/GitHub/ECE4810J_FA2021/Lab1/Zynq_CPU_wrapper_hw_platform_1/export/Zynq_CPU_wrapper_hw_platform_1/Zynq_CPU_wrapper_hw_platform_1.xpfm standalone_ps7_cortexa9_0 D:/Documents/GitHub/ECE4810J_FA2021/Lab1/hello_rtl_multiplier_system/Debug/system.bif
sdcard_gen –xpfm D:/Documents/GitHub/ECE4810J_FA2021/Lab1/Zynq_CPU_wrapper_hw_platform_1/export/Zynq_CPU_wrapper_hw_platform_1/Zynq_CPU_wrapper_hw_platform_1.xpfm –sys_config Zynq_CPU_wrapper_hw_platform_1 –bif D:/Documents/GitHub/ECE4810J_FA2021/Lab1/hello_rtl_multiplier_system/Debug/system.bif –bitstream D:/Documents/GitHub/ECE4810J_FA2021/Lab1/hello_rtl_multiplier/_ide/bitstream/Zynq_CPU_wrapper_hw_platform_1.bit –elf D:/Documents/GitHub/ECE4810J_FA2021/Lab1/hello_rtl_multiplier/Debug/hello_rtl_multiplier.elf,ps7_cortexa9_0
creating BOOT.BIN using D:/Documents/GitHub/ECE4810J_FA2021/Lab1/hello_rtl_multiplier/_ide/bitstream/Zynq_CPU_wrapper_hw_platform_1.bit
Error intializing SD boot data : Software platform XML error, sdx:qemuArguments value “Zynq_CPU_wrapper_hw_platform_1/qemu/qemu_args.txt” path does not exist D:/Documents/GitHub/ECE4810J_FA2021/Lab1/Zynq_CPU_wrapper_hw_platform_1/export/Zynq_CPU_wrapper_hw_platform_1/sw/Zynq_CPU_wrapper_hw_platform_1/qemu/qemu_args.txt, platform path D:/Documents/GitHub/ECE4810J_FA2021/Lab1/Zynq_CPU_wrapper_hw_platform_1/export/Zynq_CPU_wrapper_hw_platform_1, sdx:configuration Zynq_CPU_wrapper_hw_platform_1, sdx:image standard
make: *** [makefile:39: package] Error 1
10:48:48 Build Finished (took 5s.544ms)

Under Zynq_CPU_wrapper_hw_platform_1\export\Zynq_CPU_wrapper_hw_platform_1\sw\Zynq_CPU_wrapper_hw_platform_1, create a new folder called qemu, and create a new TXT file called qemu_args.txt under qemu folder. Just leave it empty (you may find another existing qemu_args under standalone_ps7_cortexa9_0\qemu folder).
Finally, we solved this problem.