# Develop a Boolean equation for overflow detection

Overflow Detection

1. Overflow Condition

Arithmetic operations have a potential to run into a condition known as overflow. Overflow occurs with respect to the size of the data type that must accommodate the result. Overflow indicates that the result was too large or too small to fit in the original data type. When two signed 2’s complement numbers are added, overflow is detected if:

both operands are positive and the result is negative, or both operands are negative and the result is positive.

When two unsigned numbers are added, overflow occurrs if
there is a carry out of the leftmost bit.

2. Binary Arithmetic

Computers don’t know the difference between signed and unsigned binary numbers. This is a good thing, because it makes logic circuits fast. This is also a bad thing, because distinguishing between signed and unsigned is our responsibility. The distinction is very important when detecting an overflow after addition or subtraction. Correct approach to detect the overflow is to consider two separate cases:

Let’s first solve the problem for addition of one-bit quntities:

```     0 + 0 =  0
0 + 1 =  1
1 + 0 =  1
1 + 1 = 10
```

The last line indicates that we have a carry output. That is, one-bit quantity cannot accommodate (1 + 1). Therefore, larger data type is required for (1 + 1) to succeed. When multi-bit unsigned quantities are added, overflow occurrs if there is a carry out from the leftmost (most significant) bit.

4. Overflow Detection Circuit for Unsigned Addition

Overflow detection circuit for unsigned binary addition:

Consider overflow detection when adding two one-bit signed quntities. Although one bit is required to represent the data, another bit has to represent the sign. Therefore, two-bit data type is required:

BINARY DECIMAL
sign bit data bit
0 0 0
0 1 1
1 1 -1
1 0 -2
Recall that to represent 2’s complement negative number, we must

6. The Full Adder Truth Table

Recall the truth table for the 2’s complement full adder logic:

INPUTS OUTPUTS
A B CARRY IN CARRY OUT SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

The truth table includes five columns with three inputs and two outputs.

input A input B carry IN for the current column resulting carry OUT (carry-over), generated for the next column the resulting SUM.

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

The full adder knows nothing about the difference between signed and unsigned numbers. In 2’s complement binary representation, the sign bit is simply the leftmost, or most significant, bit of the data type. The full adder circuit will be adding the sign bit column just as any other bit.

8. The Overfow Output

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign OVERFLOW
0 0 0 0 0 ?
0 0 1 0 1 ?
0 1 0 0 1 ?
0 1 1 1 0 ?
1 0 0 0 1 ?
1 0 1 1 0 ?
1 1 0 1 0 ?
1 1 1 1 1 ?

Full adder truth table for the sign bit can be extended to include new output which indicates if overfow condition has occured. Our task is to populate the OVERFLOW column with corresponding values.

Two-bit signed data type:

BINARY DECIMAL
sign bit data bit
0 0 0
0 1 1
1 1 -1
1 0 -2

Notice that when operands have opposite signs, their sum will never overflow:

```    1 + -2 = -1
1 + -1 = 0
```

Therefore, overflow can only occur when the operands have the same sign:

```      1 + 1 = 2
-2 + -2 = -4
-2 + -1 = -3
```

None of the results  { 2, -4, -3 }  can fit into the two-bit signed data type.

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign OVERFLOW
0 0 0 0 0 ?
0 0 1 0 1 ?
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 0 ?
1 1 1 1 1 ?

When operands have opposite signs, their sum will never overflow.

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign OVERFLOW
0 0 0 0 0 0
0 0 1 0 1 ?
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 0 ?
1 1 1 1 1 0

There is no overflow, if:
both operands are positive and the sum is positive. both operands are negative and the sum is negative.

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign OVERFLOW
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

When two signed 2’s complement numbers are added, overflow is detected if:

both operands are positive and the sum is negative, or both operands are negative and the sum is positive.

INPUTS OUTPUTS
Asign Bsign CARRY IN CARRY OUT SUMsign OVERFLOW
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

Notice that overflow occurs only when
CARRYin ≠ CARRYout or simply
V = Cin XOR Cout where V is the overflow signal.

14. Overflow Detection Circuit for 2’s Complement Addition

Overflow detection circuit for 2’s complement addition