Problem Description:
The following problems occur when using HLS to synthesize or package IP
error: [impl 213-28] failed to generate IP
command ‘ap_ Source ‘returned error code
has been tested in HLS of three versions (2018.3, 2020.1 and 2020.2) successively, and all errors are reported. The existing solutions (modifying the file name) do not work
Solution:
Adjust the system time of window to be less than or equal to 2021
this problem can be solved
Problem Description:
In the BD diagram of vivado, the interrupted direct connection between my IP and PS Core
An error occurs when loading the bit file generated by vivado in pynq
Solution:
Add a concat block in the connection between PS and our own IP interrupt line, as shown in the figure below
finally, the bit file can be successfully loaded in pynq
and the final program can output correct results
This article is a summary of my study. If there are copyright or knowledge errors or problems, please contact me directly. Please leave a message
PS: Based on the principle of knowledge sharing, this blog can be reproduced, but please indicate the source!
catalogue
1. Problem description
2. Cause analysis:
3. Problem solving:
1. Problem description
When I debug the project, in order to capture the signal value to observe the timing, I added ILA, and then encountered vivado error when generating bitstream. The warning is as follows:
The specific error contents are as follows:
[DRC LUTLP-1] Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop.
This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is u_DdrRdData/NxtRdState[0]. Please evaluate your design. The cells in the loop are: u_DdrRdData/NxtRdState_inferred_i_3, and u_DdrRdData/NxtRdState_inferred_i_8.2. Cause analysis:
As shown in the code segment below, the combinational loop is combinational logic, which feeds back to itself without registers. The simplest example is an inverter whose output is fed back to the input to produce an oscillator.
Therefore, the combined logic signal nxtrdstate for the state machine cannot be used for ILA grabbing!!!
At the same time, the error can be prompted in the warning message of vivado tool:
This warning is described in ug901 as follows:
3. Problem solving:
Do not use ILA to grab the signal value assigned in the combinatorial logic of the state machine!!!
This article is a summary of my study. If there are copyright or knowledge errors or problems, please contact me directly. Please leave a message
PS: Based on the principle of knowledge sharing, this blog can be reproduced, but please indicate the source!
1. Problem description
The vivado error problem warning is as follows:
[DRC NSTD-1] Unspecified I/O Standard: 1 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SYS_CLK.
The IO setting interface is as follows:
The IO working voltage is not clearly defined, so the following operations are required;
2. Solution:
Create a new. TCL file and write the following contents:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]Add in vivado setting:
The error warning disappears after recompilation!