Tag Archives: FPGA Development

[Solved] Quartus II waveform simulat error: error: waveform2 vwf. VT (30): near “,” syntax error, unexpected “, ‘# * * error

I. problem
when quartus is used to design 4 frequency divider based on D trigger, the following errors occur in waveform simulation:

 Error: Waveform2.vwf.vt(30): near ",": syntax error, unexpected ','
# ** Error: D:/Quartus/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./D4.do line 4
Error.

II. Solution

in the schematic design, my input and output ports are named input and output respectively. That’s the mistake. We just have to name it something else. For example: CLKIN, out. Then recompile and no error will be reported during simulation. The correct simulation diagram is as follows:

[Solved] PYNQ load bit error: KeyError: ‘interrupts‘

Problem Description:

In the BD diagram of vivado, the interrupted direct connection between my IP and PS Core

An error occurs when loading the bit file generated by vivado in pynq

Solution:

Add a concat block in the connection between PS and our own IP interrupt line, as shown in the figure below

finally, the bit file can be successfully loaded in pynq

and the final program can output correct results