Pay attention to check the error prompts, which will generally tell you where to find the reason. Assignment under multiple single edges is not supported

Let’s look at your code. Where is edge related? (posedge sclk or posedge reset)

That’s how we usually use it,

always @ (posedge clk or posedge reset) 

if (reset == 1’b1)

….

else

Reset is the reset signal,

If your code doesn’t have the following reset part, it will think that this is a clock sampling, and multiple clocks will take the same data, so it will report an error.