Cause

When porting PS2 code for the project, I thought it was a simple thing. I closed it for several hours. The data I read has been incorrect (the data beat is unstable). I decided to give up, but I still decided to step on the pit to the end! So there is this article

Solution direction

Based on the previous experience of pit drainage, the problems may lie in the following places

1. hardware problem IO port configuration, clock tree configuration and timer configuration. The underlying driver code is not suitable (the widely circulated code is F103 version)

Problem exploration

1. 1. hardware problem

 

1. 1. an F103 board was found and driven normally. The problem of PS2 damage and wire open circuit was eliminated. IO port configuration

 

1. 1. the IO port configured according to the official routine, tested that the output of each IO port is normal, and tried to modify the speed of the IO port, which is useless. The underlying driver code is not adapted to the

 

1. 1. PS2 driver code. Only the following lines refer to the underlying

#define DI    HAL_GPIO_ReadPin(PS2_DAT_GPIO_Port,PS2_DAT_Pin) 
#define DO_H  HAL_GPIO_WritePin(PS2_CMD_GPIO_Port,PS2_CMD_Pin,GPIO_PIN_SET)     
#define DO_L  HAL_GPIO_WritePin(PS2_CMD_GPIO_Port,PS2_CMD_Pin,GPIO_PIN_RESET)     
#define CS_H  HAL_GPIO_WritePin(PS2_CS_GPIO_Port,PS2_CS_Pin,GPIO_PIN_SET)      
#define CS_L  HAL_GPIO_WritePin(PS2_CS_GPIO_Port,PS2_CS_Pin,GPIO_PIN_RESET)     
#define CLK_H  HAL_GPIO_WritePin(PS2_CLK_GPIO_Port,PS2_CLK_Pin,GPIO_PIN_SET)   
#define CLK_L  HAL_GPIO_WritePin(PS2_CLK_GPIO_Port,PS2_CLK_Pin,GPIO_PIN_RESET)  

Check the macro definition of each IO port to correspond to the IO port on the board. Delay is also used in many places in the source code_ms/delay_US function uses a mature timer library to ensure the accuracy of delay, so this problem is also eliminated
4. Timer configuration
unlike F1, which uses TIM4 as the internal clock, F4 uses tim5, but both are ordinary timers and have no essential difference, so the problem is obviously not here
5. Clock tree configuration
finally, the problem is located here
referring to the official routine, change the master clock frequency from 180mhz to 72mhz. It is normal
in other words, PS2 has high requirements for communication timing. The maximum clock frequency of F4 will accelerate the communication frequency, which may lead to the collapse of some protocols, so the data is unstable.

Prospect

Of course, the optimal solution is not to change the clock frequency of the chip, which will affect the execution rate of other programs. Theoretically, the timing can be restored to normal by adding a certain delay operation to the driver code, but I didn’t do it because of time. I hope interested players can have an in-depth study, and it’s best to share the code. (not found on the Internet at present)